With densification of semiconductor devices represented by dynamic random access memory (DRAM) and the like, the occupancy area of various components that configure the semiconductor device is being reduced. With semiconductor devices that adopt a configuration that layers a plurality of components, the reduction of the occupancy area of each component decreases an overlapping margin that permits position shift of components on a lower layer and components on an upper layer in the production process. A shortage of overlapping margins causes problems such as a reduction of contact area due to position shift and an increase in contact resistance by such reduction, as well as disconnection, when the overlapping component is a conductor such as a contact plug.
As one related technology to resolve the above problem, there is the method for producing a semiconductor device disclosed in Japanese Unexamined Patent Application Publication No. 2007-150083 (Patent Document 1).
In this method, first, a (second) interlayer insulating film, an etch stop film, and a (third) interlayer insulating film are layered in order on a (first) interlayer insulating film having a contact plug formed thereon. Next, to form a through-hole that reaches the contact plug, an upper portion of the through-hole is formed on the (third) interlayer insulating film and the etch stop film through anisotropic etching. After forming an etch protective film on a side wall of the upper portion of the through-hole, a lower portion of the through-hole is formed on the (second) interlayer insulating film through isotropic etching. The lower portion of the through-hole formed in this manner has a larger diameter compared to the upper portion. As a result, a contact area between the contact plug and a via plug formed in the through-hole can be larger, and contact resistance therebetween can be reduced.